1. Field of Invention
The present invention relates to a spread spectrum clock generating circuit for reducing an electromagnetic interference (EMI) noise.
2. Description of Related Art
An EMI noise is an electromagnetic noise emitted from an electronic device. When the EMI noise is enhanced, it generally has a negative influence on any peripheral devices. Accordingly, for each frequency band, a regulation level is established. A common digital electronic device operates by clocks having a predetermined frequency. Normally, the clocks are in rectangular waveform, so that not only a fundamental wave noise, but also second and higher harmonics component noises are generated. In order to prevent these noises, a particular measure is generally required.
Conventionally, an analog PLL (phase-locked loop) circuit is used as a spread spectrum clock generating circuit in order to prevent EMI noise. However, as a result, a period in frequency variation is increased and accumulative delays for fundamental waves are increased. Therefore, the analog PLL circuit is generally not suitable for use in a semiconductor integrated circuit.
Accordingly, considering an application such as, for example an ASIC (application specific integrated circuit) or the like, the spread spectrum clock generating circuit shown in FIG. 4 has been proposed (see, for example, PCT International Publication WO00/45246). Referring to FIG. 4, a delay circuit 50 is constituted by delay buffers 51 to 54 which are cascade-connected to an input clock signal CLKIN. A selective circuit 60 receives the clock output from the delay buffers 51 to 54 in the delay circuit 50 and selects one clock as an output clock CLKOUT. A control circuit 70 receives a delayed clock signal because the clock output from the delay buffer 54 at the final stage is delayed by a delay buffer 71 in the selective circuit 60. The control circuit 70 also controls a selective operation of the selective circuit 60 by using predetermined bit signals.
In the clock generating circuit shown in FIG. 4, the control circuit 70 supplies the selective circuit 60 with combined bit signals so as to cycle in a predetermined period, and a clock period is increased or decreased by the combined bit signals, whereby the period of the output clock CLKOUT can be increased or decreased and a frequency spectrum distribution can thus be spread. This generally results in the reduction of an EMI noise.
The clock generating circuit in FIG. 4 uses the delay circuit 50, which has plural output terminals. Thus, at connection points (output points) in post-stages of switch portions of the selective circuit 60, there are generally large parasitic capacitive loads. Accordingly, the ability of the delay buffers 51 to 54 to drive the output terminals must be increased. This causes various problems such as, for example, an increase in circuit area, an increase in power consumption, and increased jitter due to an increased minimum delay step. The jitter means that modulation is performed beyond frequency modulation required for EMI-noise prevention, and clock performance is thus affected.